Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates generally to computer systems and, more particularly, to a new use of the IEEE 1394 Peripheral Interface Bus. Still more particularly the present invention relates to implementation of the IEEE 1394 Peripheral Interface Bus as an internal computer bus, rather than its intended application as a high speed external peripheral serial interconnect bus.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modern computer systems. Early computer systems had relatively few components. As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a xe2x80x9cbus.xe2x80x9d
As computer technology evolved, it became common to connect additional peripheral devices to the computer to provide greater functionality. FIG. 1 shows a representative prior art computer system that includes a CPU coupled to a bridge logic unit via a CPU bus. The bridge logic unit is sometimes referred to as a xe2x80x9cNorth bridgexe2x80x9d for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a PCI bus or other expansion bus (such as an EISA bus). The North bridge interconnects and controls the flow of information between the CPU, the memory, the PCI bus, and other buses and devices as desired. Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
The various buses shown in FIG. 1 allow the internal subsystems of the computer system to communicate. Use of different bus architectures such as PCI bus, AGP bus, and CPU bus results in an added layer of complexity caused by remapping of signal lines and increased complexity of the North bridge chip. Furthermore, each bus experiences performance bottlenecks, causing the overall performance of the computer system to degrade. For example, the PCI bus architecture is a parallel bus architecture in which multiple bytes of data are transferred in parallel. The PCI bus architecture permits data transfer rates between 33 MHz up to a maximum of 66 MHz. Thus, the computer system may be forced to operate at a maximum clock speed of 66 MHz even if all other buses and hardware operate at a much higher clock speed. Furthermore, because the PCI bus architecture permits only 32 bits of data to pass during a clock cycle, other components can only process 32 bits of data in a clock cycle even though the component is capable of much higher processing. The electrical design of the computer system is made more complex because the electrical characteristics of each bus may vary. For example, the design of a computer system that supports the PCI, AGP, and CPU bus requires that each data line corresponding to a bit be impedance matched to chips coupled to the bus. Data lines in each of the buses may have different impedance matching requirements resulting in extremely complex bridging circuits. Furthermore, each type of bus may also have specific timing requirements that are very tight toleranced and bridging of these timing requirements may result in lost clock cycles and complex bridging circuits.
One solution that reduces the complexity of computer system design caused by the use of a large number of different buses is to replace the PCI bus with a generic busing architecture that is capable of attaching to preexisting peripheral devices. Such a generic bus would couple to the North Bridge and ideally be able to directly connect to a large number of peripheral devices. Despite the simplification of the computer system design along with the apparent performance advantages of such a system, to date no such system has been implemented.
The problems noted above are solved in large part by a computer system that includes a computer chassis containing an IEEE 1394 bus and peripheral devices. The computer system preferably further includes a CPU, a memory, and a bridge logic unit coupling the CPU to the memory. Peripheral devices in the computer system chassis couple to the bridge logic unit through the IEEE 1394 bus. Some exemplary peripheral devices include a mouse, a fiber optic device, a docking station, a Compact Disc-Rewritable (xe2x80x9cCD-RWxe2x80x9d) device, a Digital Versatile Disc (xe2x80x9cDVDxe2x80x9d) device, a Floppy Disk Drive (xe2x80x9cFDDxe2x80x9d) device, and an IEEE 1394 external connector.
In one exemplary embodiment, a PCI-to-IEEE 1394 adapter couples the bridge logic unit to the peripheral devices. The bridge logic unit connects to the PCI-to-IEEE 1394 adapter through a PCI bus and the PCI-to-IEEE 1394 adapter connects to the peripheral devices through an IEEE 1394 bus. Preferably, the PCI-to-IEEE 1394 adapter includes a PCI interface coupled to the PCI bus and an IEEE 1394 interface coupled to the IEEE 1394 bus. Queue storage elements connect the PCI interface and IEEE 1394 interface.
In another exemplary embodiment, the bridge logic unit includes the functionality of the PCI-to-IEEE 1394 adapter and directly connects to the peripheral devices in the computer system chassis. A memory bus couples the memory to the bridge logic unit and a CPU bus couples the CPU to the bridge logic unit. The bridge logic unit includes a memory controller, a CPU interface, an IEEE 1394 interface and an AGP interface. The IEEE 1394 interface in the bridge logic unit couples to the IEEE 1394 bus and the AGP bus couples a graphics controller to the bridge logic unit. The bridge logic unit includes a plurality of queue storage elements that couple the IEEE 1394 interface to the memory controller, CPU interface, and AGP interface.